| Development of Resynthesis Flow for Improving Logical Masking Features of Combinational Circuits |
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| Authors |
| | Nadolenko V.V. |
| | Telpukhov D.V. |
| | Bitkov U. |
| Date of publication |
| | 2018 |
| DOI |
| | 10.31114/2078-7707-2018-1-50-56 |
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| Abstract |
| | the following paper is devoted to the elaboration of resynthesis flow for combinational circuits in order to improve fault tolerance. Sensitivity factor which is an average number of unreliable components is used as a metric for circuit's vulnerability to single event transients (SETs). Resynthesis algorithm initiates an iterative process of improving a part of original circuit by substituting it with a functionally equivalent subcircuit of alternative structure providing better masking features. Subcircuit optimization with respect to its reliability doesn't necessarily involve redundancy. Actually, redundant structure may not provide the best result. Each subcircuit is evaluated separately in order to speed up the process. Input pattern probabilities and output observabilities are used during the evaluation to simulate the environment influence. Proposed algorithm was tested on circuits from ISCAS’85 and LGSynth’89 benchmarks synthesized in Synopsys Design Compiler with area and timing optimization using nangate and silterra libraries. |
| Keywords |
| | SET, resynthesis, fault tolerance, observability, ODC |
| Library reference |
| | Nadolenko V.V., Telpukhov D.V., Bitkov U. Development of Resynthesis Flow for Improving Logical Masking Features of Combinational Circuits // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 1. P. 50-56. doi:10.31114/2078-7707-2018-1-50-56 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2018/pdf/D038.pdf |
