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Development of Methods for Genetic Synthesis of Fault-Tolerant Logic circuits
Authors
	Telpukhov D.V.
Date of publication
	2018
DOI
	10.31114/2078-7707-2018-1-45-49
Abstract
	Fault tolerance of electronic equipment is now being given special attention. This is facilitated by the expansion of application of integrated circuits, coupled with an increase in the permissible limits of destabilizing effects that increase the vulnerability of integrated circuits. At present, at the development stage, it is often necessary to take into account the requirements for fault tolerance and apply various methods and tools for developing the most stable circuits. The article presents a method for synthesizing fault-tolerant logic circuits based on a genetic algorithm. The basic structure of the algorithm, as well as some details concerning data representation and genetic operators are described. The fitness function of the algorithm accounts for the failure metric of the combinational circuit, which characterizes the average number of unreliable elements, that is, the elements whose error affects the outputs of the circuit. For representation in the form of a chromosome, an ordered linear representation of the combinational circuit was developed. The basic element in this representation is the structure that combines the element type and links to the elements connected to the inputs. However, instead of labels, the position of the element in the array of elements is used. Such a representation made it possible to simplify a number of genetic operators, as well as to cross chromosomes of different lengths. The method shows good convergence for small circuits. Selection is first carried out by the parameter of the proximity of the function to the reference one, after which the metric of fault tolerance begins to be taken into account. However, the applicability of the method is limited to schemes of small size.
Keywords
	evolutionary synthesis, fault-tolerance, combinational circuits, genetic algorithms
Library reference
	Telpukhov D.V. Development of Methods for Genetic Synthesis of Fault-Tolerant Logic circuits // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 1. P. 45-49. doi:10.31114/2078-7707-2018-1-45-49
URL of paper
	http://www.mes-conference.ru/data/year2018/pdf/D037.pdf