| Development of FPGA Project for Microprocessor Prototype Module |
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| Authors |
| | Petrov A.N. |
| | Yurlin S.V. |
| Date of publication |
| | 2018 |
| DOI |
| | 10.31114/2078-7707-2018-3-45-51 |
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| Abstract |
| | this article is an overview of a FPGA project development for a module of distributed hardware emulation system used by JSC «MCST» with use of Intel Stratix 10 GX and Xilinx Virtex UltraScale architectures. The employment of multi-FPGA hardware emulation approach raises several problems: necessity to transfer big volumes of data between modules, requirement to finish the transfer within one emulation cycle and need to create several FPGA projects for different module functionality. The problem of big volume transfer is solved by usage of double serialization of data: in designated SerDes of one inter-FPGA line and in transmitter IP-core of interface. The requirement of one emulation cycle transfer is adhered by using 16-bit LVDS interface, hardware implementation of which has low processing latency and acceptable bandwidth. The multi-project problem is solved via introduction of base project, which is universal for all modules with same FPGA and has all common modules for every project: interface IP-cores and inter-FPGA line controllers. This project acts as a template for further development of projects for modules of desired functionality. The task of creating pin assignments is overviewed with creating a general workflow and examples for aforementioned FPGAs. |
| Keywords |
| | emulation, prototype, FPGA, microprocessor, KUB-PRO. |
| Library reference |
| | Petrov A.N., Yurlin S.V. Development of FPGA Project for Microprocessor Prototype Module // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 3. P. 45-51. doi:10.31114/2078-7707-2018-3-45-51 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2018/pdf/D031.pdf |
