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Delta-Sigma Modulator with 10 MHz Clock Frequency in 180 nm CMOS Technology
Authors
	Pilipko M.M.
	Morozov D.V.
	Yenuchenko M.S.
Date of publication
	2018
DOI
	10.31114/2078-7707-2018-4-44-48
Abstract
	Analog-to-digital converters (ADC) based on delta-sigma modulation [1-3] have low power consumption and low chip area in comparison with other ADCs. A delta-sigma ADC consists of a modulator and a decimation filter. The modulator converts the analog input signal into the output bit stream. This bit stream is filtered and decimated by the filter. Decimation filters are digital circuits described in [2-4]. General characteristics of the delta-sigma ADC depend on the modulator characteristics. Therefore, the design of the delta-sigma modulator is a critical issue. In this paper, an integrated circuit of the delta-sigma modulator is discussed. For a test chip fabrication UMC 180 nm mixed mode/RF 1P6M technology was used. A typical solution for delta-sigma ADCs is the second or higher order modulator. In this work the second order balanced delta-sigma modulator proposed in [5] is used. The modulator consists of two integrators, a comparator, a feedback and feedforwards. Each integrator is a switched-capacitor circuit. An amplifier used in the integrators is an operational transconductance amplifier (OTA). The OTA circuit is presented in [6]. The comparator circuit is described in [7]. Typically there are only feedbacks in the delta-sigma modulator. The modulator output code is a response to the input signal that was two clock cycles earlier. Therefore, signals that go to integrators contain not only a difference between the modulator input signal and a signal corresponding to the output code but also a highpass-filtered version of the input signal. Integrators restore this signal to a full amplitude. Because of nonlinear OTA gain and slew-rate effects, harmonic components of the input signal are created at the outputs of the integrators, and, as consequence, in the modulator output code. The proposed circuit uses a feedforward from the modulator input and the first integrator output to the comparator input. Thus, the two clock cycle delay between the input signal and the circuit response is eliminated. The input signal of integrators has only a difference between the modulator input signal and the signal corresponding to the output code. Signal amplitudes at outputs of the integrators are significantly less than in the typical structure, as consequence, non-linear distortion of the output signal is decreased. Simulation of OTA was performed with a 7 pF load on each output. Characteristics of OTA are as follows. DC gain is 60 dB. The unity gain frequency is 173 MHz. Phase margin is 81°. The main characteristic of the delta-sigma modulator is signal-to-noise and distortion ratio. The output spectrum of the modulator was obtained for the balanced harmonic input signal of 38.758 kHz with an amplitude of 0.5 V by post-layout simulation. The dynamic range of the modulator is 74.6 dB, so ADC can achieve resolution of 12 bit. The integrated circuit of the delta-sigma modulator was designed for UMC 180 nm CMOS technology and fabricated through Europractice IC service. The modulator occupies 400×250 μm2 without ESD ring and pads. A tunable 3-rd order Chebyshev low-pass filter was designed based on switched-capacitor circuits for the same technology. The filter has the dynamic range no less than 74 dB. The cutoff frequency is 40 kHz for the clock frequency of 4 MHz. Measurements were organized as follows. The 10 MHz clock frequency signal of the modulator was generated by Agilent 81130À. A test harmonic signal was provided to the filter input from Agilent 81150A. The filter output was connected to the input of the modulator. The modulator output signal was acquired by Agilent 16802A (logic analyzer). A signal from the logic analyzer was processed in MATLAB to obtain the modulator output spectrum. Measurements have shown that the dynamic range of the modulator is 72.3 dB for the 38.758 kHz input signal. Power consumption of the modulator is up to 5.7 mW with a 1.8 V supply voltage. The modulator suits as a part of calibration systems.
Keywords
	delta-sigma modulator, switched-capacitor circuits, operational transconductance amplifier.
Library reference
	Pilipko M.M., Morozov D.V., Yenuchenko M.S. Delta-Sigma Modulator with 10 MHz Clock Frequency in 180 nm CMOS Technology // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 4. P. 44-48. doi:10.31114/2078-7707-2018-4-44-48
URL of paper
	http://www.mes-conference.ru/data/year2018/pdf/D020.pdf