| SsVER - system of synthesis and verification of combinational logic schemes |
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| Authors |
| | Bibilo P.N. |
| | Kardash S.N. |
| | Romanov V.I. |
| Date of publication |
| | 2006 |
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| Abstract |
| | The system of synthesis and verification of multioutput combinational circuits in basis of libraries of designing of base matrix crystals is described. Initial data are matrix and parenthesis descriptions of systems of boolean functions, and also descriptions in language VHDL. System SsVer is joined with system of synthesis LeonardoSpectrum and has programs of logic minimization and the verifications which are absent in LeonardoSpectrum. Sharing SsVer and LeonardoSpectrum allows to get the logic circuits having smaller complexity and a delay. |
| Keywords |
| | synthesis and verification of combinational logic schemes |
| Library reference |
| | Bibilo P.N., Kardash S.N., Romanov V.I. SsVER - system of synthesis and verification of combinational logic schemes // Problems of Perspective Microelectronic Systems Development - 2006. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2006. P. 45-50. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2006/06.pdf |
