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Structure and Algorithm Development of Built-in Self-repair for SRAM
Authors
	Shchigorev L.A.
Date of publication
	2018
DOI
	10.31114/2078-7707-2018-2-123-129
Abstract
	Experts from the Semico Research Corp group estimate that in the near future up to 75% of the area of modern system-on-chips (SoC) will be occupied by elements of static random access memory (SRAM). Therefore, in the process of developing memory subsystems, it is necessary to add redundant memory elements. It’s the most commonly used technic for memory yield improvement. But if the existing redundancy was not used so, in the future it can be used for the replacement of the faulty cells. Also, for integrated circuits manufactured using sub-100-nm process, the availability of spare elements helps to level out the sharp growth of the failing SRAM cells number with the operating voltage reducing. To be able to reconfigure memory during operation only soft repair method can be used. This article is devoted to the repair of SRAM with redundant columns. Two methods of substitution are considered: shift and multiplexing. When using a shift, the memory block is divided into areas whose elements can be replaced by a single spare one. When multiplexing is used, the replacement takes place according to the principle of "anyone on any", i.e. any basic element can be replaced by any reserve element. The self-repair operation is preceded by the self-testing operation. The method of redundancy analysis depends on the way of the built-in self-test (BIST) status information producing. The proposed built-in self-repair (BISR) scheme interacts with the BIST unit, which has only single-bit status signal. Therefore, the search of CRV is executed by using the exhaustive search. The equations for calculating the maximum number of self-test operations are presented in the article. For reducing the maximum number of test iterations, the word width dividing is provided. Improved structure and algorithm for the device self-repair is presented in the article. For the area and timing penalties estimation 4Kx128 memory block was selected. 5 variants of memory organization were investigated: consisting from 8, 16, 32, 64 and 128-bit arrays. All blocks have two redundant columns – one column per each half of the word. BISR block was written in Verilog HDL. Functional modeling and synthesis for the for 28 nm process CMOS were carried out. The absolute values of the areas occupied by the BISR and BIST are presented, as well as the maximum values of the delays on critical paths. It is shown that the additional area costs for the redundant memory elements and the BISR and BIST units do not exceed 18%.
Keywords
	memory repair, memory repair analyzer, self-test, system-on-chip (SoC), redundancy, spare columns, SRAM.
Library reference
	Shchigorev L.A. Structure and Algorithm Development of Built-in Self-repair for SRAM // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 2. P. 123-129. doi:10.31114/2078-7707-2018-2-123-129
URL of paper
	http://www.mes-conference.ru/data/year2018/pdf/D017.pdf