| A Parasitic Resistance Extraction Method for Early Analysis of Complex Shaped Power Delivery Networks |
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| Authors |
| | Malinauskas K.K. |
| Date of publication |
| | 2018 |
| DOI |
| | 10.31114/2078-7707-2018-1-161-166 |
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| Abstract |
| | With growing complexity and transistor density of modern electronic devices power integrity has become a key design factor [1]-[2]. Power supply constraints such as IR drop should be considered well before the signoff in physical design flow. In early design experiments essential is to use fast but reasonably accurate verification tools. Such re-quirements become tough for early IR-drop analysis when power delivery networks (PDN) with irregular topologies are considered. This is because traditional resistance extraction approaches apply either heavy field solvers on fine meshes or analytical heuristics with non-trivial and ambiguous polygon decomposition [5]-[9]. This work presents a novel method of parasitic resistances extraction from arbitrary shaped 2D interconnects. It includes a new approach to resistor network construction based on medial axis transform [11] and a sim-ple set of analytical formulas for resistance values estimation. The extracted circuits are compact enough though are natu-rally mapped to the original complex layout. That is useful for early power delivery modeling with voltage drop or equivalent resistance maps visualization. The method is im-plemented within early design stage power integrity analysis system Silvaco Invar Prime [12]. It showed high efficiency in terms of runtime and memory consumption of the whole simulation flow while keeping sufficient accuracy. The ex-traction itself generates circuits of O(n) size in O(n log n) time where n is the number of points describing the input geometry plus the number of interlayer contacts. We bench-marked our extractor against the tiling heuristics [1] adapted to complex polygons and observed the equivalent resistances correlation within 5–15%. At once the circuit sizes and IR-drop simulation runtimes reduced by an order of magnitude, the consumed memory – around 2x. The new approach can be applied to a variety of designs with complex PDN layout such as analog and mixed signal VLSI or printed circuit boards. |
| Keywords |
| | resistance extraction, power integrity, voltage drop, Voronoi diagram, medial axis |
| Library reference |
| | Malinauskas K.K. A Parasitic Resistance Extraction Method for Early Analysis of Complex Shaped Power Delivery Networks // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 1. P. 161-166. doi:10.31114/2078-7707-2018-1-161-166 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2018/pdf/D009.pdf |
