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Development of Real Number Models of Analog IP Blocks for Mixed Signal SoC Verification
Authors
	Bobkov P.G.
	Bragin K.R.
Date of publication
	2018
DOI
	10.31114/2078-7707-2018-1-89-96
Abstract
	Due to increasing complexity of very-large-scale integration (VLSI) circuits, standard SPICE and Fast SPICE full chip simulation cannot deliver a verification arrangement on time. This leads to growing necessity of methodology for accurate and fast verification of mixed signal (AMS) designs. The article focuses on modern approaches based on using behavioral model of IP blocks for mixed signal system on chip (SoC) verification on system level. A novel approach for AMS simulation, which uses Real Number Modeling (RNM) concepts, is considered. RNM is a special technique used to model electrical signals by representing them as floating-point real values based on discrete event. It is allow to describe analog block as a signal-flow model and then to simulate it in a digital solver. RNM is available in the Verilog-AMS, SystemVerilog, VHDL, e. So complex mixed signal IP blocks can be integrated into common verification environment as real number models, which can be used in metric-driven verification bringing its techniques such as randomization, coverage and asserts. Developed behavioral models of typical analog block with simple digital control logic – programmable gain amplifier – are presented in this article in terms of different abstract level. Syntactic features, main advantages and disadvantages are analyzed in comparison with RN-model in Verilog-AMS language, named wreal model. Its key benefits are a much faster simulation speed relative to analog models and more accuracy relative to digital models. This significantly reduces the verification time for mixed signal full chip simulations. In addition, the advantages of this approach are illustrated by taking complex analog IP blocks of CMOS/LVDS receiver and transmitter as examples, which are parts of a real SoC design. RN-models using wreal type have been designed successfully with comparison of its spice electrical model. The calibration procedure was used to adjust the model parameters within Cadence Virtuoso design environment Schematic Model Generator (SMG) and AMS Design & Model Validation (amsDmv). The functionality of IP has been verified by using different functionality check test cases. Developed RN models makes it possible to behaviorally model analog effects, such as supply ramp behavior, PVT variations, complex mechanism for the formation of adjustable delay, output impedance, influence of supply voltage on output CMOS and LVDS levels, shutdown behavior using event driven digital simulators. RNM shown in this work is compatible with existing digital verification techniques. Modern UVM methodology can be extend for supporting analog verification. The extended methodology, named UVM-MS, include verification planning for analog blocks, analog signal generation, checking and assertion techniques for analog properties and analyzing analog functional coverage. These features in combination with high-level modeling of analog circuits using RNM are the powerful reusable instruments for the complex mixed signal IP level and SoC level verification.
Keywords
	Model, verification, mixed signal simulation, IP, SoC, Verilog-AMS, RNM, wreal, UVM-MS.
Library reference
	Bobkov P.G., Bragin K.R. Development of Real Number Models of Analog IP Blocks for Mixed Signal SoC Verification // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 1. P. 89-96. doi:10.31114/2078-7707-2018-1-89-96
URL of paper
	http://www.mes-conference.ru/data/year2018/pdf/D001.pdf