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Practical Aspects of Design Verification of Complex Chips
Authors
	Sokhatski A.A.
Date of publication
	2016
Abstract
	Complex multi-billion up-to-date chips, with significant number of internal blocks require consistent Design Verification (DV) methodology across blocks and functional groups of blocks (clusters). It will simplify integration, horizontal and vertical reuse, switching resources and certainly will contribute in increasing quality and decreasing time to market. Consistent flow should cover DV from design spec review up to chip bring up in the lab and further support. The paper considers constraint random simulation with further code, functional and assertion coverage closure as the main DV approach and goes through important practical aspects from the author’s experience at Cisco Systems Inc.: 1) DV Environment basics focusing on what is done on the top of industry standard Universal Verification Methodology (UVM)[1]: environment structure, configuration, custom phases, company scope base classes layer, reuse component; special attention paid to components related to control plane register / memory access; 2) DV Environment Build Automation, including: assistance in building basic block DV environment components; generation of data structures for register access components set: register map, auto initialization code, interrupt error handler, end of test checker, background register access; generation done from shared source: registers description which is prepared in System RDL[2]; 3) Important DV flow steps and tools used, including build and run, regression and release flow, linting[3]. As a result of consistent flow with tools support and development automation we are getting back high quality chips and reduced development time.
Keywords
	Design Verification, RTL, SystemVerilog, UVM, SVA, System RDL.
Library reference
	Sokhatski A.A. Practical Aspects of Design Verification of Complex Chips // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 2. P. 16-23.
URL of paper
	http://www.mes-conference.ru/data/year2016/pdf/D198.pdf