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Timing analysis of digital circuits basing on logic correlations
Authors
	Glebov A.L.
	Mindeeva A.
	Sheremetov V.V.
Date of publication
	2016
Abstract
	Timing analysis is an important stage in the process of VLSI timing verification. Its aim is finding signal critical paths and calculation of maximum clock frequency for the given circuit [1, 2]. There exist multiple methods of circuit timing analysis, that may be divided into two types: dynamic and static. Dynamic methods are based on simulation of the circuit operation, for the given input testvector sequence. Various methods of this type differ only in degree of adequacy of the model under use. On the other hand, static timing analyzer is based on different principle. Instead of simulation, it consideres all possible signal paths in the circuit. This requires larger computer memory, but is orders of magnitude faster than dynamic analysis. In modern VLSI design, static timing analysis (STA) is the only method suitable for timing verification, since it is able to cope with circuits of very large size in acceptable time [3, 4]. Within STA algorithm, the directed weighted graph is processed, that corresponds to some combinational block of synchronous VLSI circuit. The aim of analysis is to detect the longest and shortest paths from primary inputs to primary outputs of the block. The result of STA algorithm is usually some specified number of most critical paths in the circuit [5]. Existing STA programs do not consider the logic structure of the circuit. Therefore, among marked critical paths there can exist the false paths, i.e. paths that do not actually propagate switching for any transitions of primary inputs. For detecting the false paths we propose here to use the logic implications, which compose the subset of all logic constraints in the ciruit [6, 7]. This allows to improve the accuracy of STA results substantially. It should be noted that, unlike the work [8], in this paper we consider not only simple logic implications (SLI), but also complex ones , i.e. triple logic implications (3-LI).
Keywords
	Static timing analysis, false paths, logic implications.
Library reference
	Glebov A.L., Mindeeva A., Sheremetov V.V. Timing analysis of digital circuits basing on logic correlations // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 1. P. 131-135.
URL of paper
	http://www.mes-conference.ru/data/year2016/pdf/D195.pdf