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Reducing area and increasing compression ratio of scan compression system for digital VLSI using stuck-at fault model
Authors
	Ladnushkin M.S.
Date of publication
	2016
Abstract
	Combinational scan compression techniques are attractive for their low impact on area and high compression ratios. These compression techniques use methods of reducing scan chains length to the minimum values to decrease testing time and volume of test data. Scan load compression techniques exploit the low density of care bits in scan load data. Scan unload compression techniques exploit the fact that error values appear more or less randomly, and only on a few scan chains at a time. But high number of scan chains causes the growth of density of Xs (number of unknowns) and higher values of significant bits during load/unload. A theoretical analysis of scan compression system built on Fully X-tolerant Combinational Scan Compression architecture was introduced. This architecture consists of load decompressor based on broadcast-scan-based scheme (MUX-based load decompressor) and unload compressor based on Steiner Triple System (XOR-based unload compressor) with X-masking logic (AND-based unload selector). Internal scan chains could be observed in 3 masking modes in dependence of density of Xs: transparent, single-fanout and direct observation modes. Analysis shows that growing number of scan chains after a certain number results in reduction of compression ratio and higher testing time. Also higher number of scan chains means bigger area overhead because the test area is growing linearly with the number on scan chains. So the effectiveness of compression in terms of compression ratio divided by area overhead should have maximum at certain number of scan chains and external channels. The method presented in this paper exploit the fact that high values of Xs density and significant bits during test lower the effectiveness of scan compression schemes. So reducing the number of scan chains could minimize the impact of scan compression system. Presented method is based on iterative seeking the optimal values of number of scan chains and number of external channels of scan architecture for testing constant faults of 250 nm digital VLSI. In the set of experimental results for two 250 nm digital VLSI designs it was shown that increasing the number of scan chains could cause rising pattern inflation during ATPG. Inflation is influenced by several factors, most notably by the restricted ability to target faults due to dependencies introduced by the load decompressor, and the effect of static and dynamic Xs. With the help of the method was found a balance between area and compression ratio. Creating scan compression structures using this method can reduce area overhead up to 5 times while compression ratio could be increased up to 2.3 times. The diagrams of effectiveness of compression and compression ratio in dependence on number of scan chains and external channels are presented. A methodology of creating scan compression architecture for 250 nm digital VLSI based on presented method was developed. It was used in creating scan compression system for 250 nm SOI VLSI “Shema-6”. Area overhead was reduced by 5 times and compression ratio was increased by 23% comparing with scan compression system with the same number of external channels and maximum number of scan chains.
Keywords
	design-for-test, scan data compression, ATPG, modeling.
Library reference
	Ladnushkin M.S. Reducing area and increasing compression ratio of scan compression system for digital VLSI using stuck-at fault model // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 2. P. 68-75.
URL of paper
	http://www.mes-conference.ru/data/year2016/pdf/D166.pdf