| Static timing analysis aware false conduct path detection in terms of logic implication |
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| Authors |
| | Solovyev R.A. |
| | Glebov A.L. |
| | Gavrilov S.V. |
| Date of publication |
| | 2006 |
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| Abstract |
| | Static timing analysis (STA) is widely used for IC timing verification. But in the most cases it lead for pessimistic overvaluation. One of the important problems of STA is false path detection. These paths cannot be realized in the circuit due to logic limitations. Existing algorithm is not used in industrial CAD due to complexity. In this article alternative approach is proposed. It lets to reveal sufficiently quantity of logic limitations and detect major part of false conduct paths accounting for logic limitations. It’s known that task of logic limitations analysis is NP-complete. As opposed to known methods, proposed approach is heuristic and has linear complexity. |
| Keywords |
| | static timing analysis, false conduct path, logic implication |
| Library reference |
| | Solovyev R.A., Glebov A.L., Gavrilov S.V. Static timing analysis aware false conduct path detection in terms of logic implication // Problems of Perspective Microelectronic Systems Development - 2006. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2006. P. 22-28. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2006/02.pdf |
