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Partitioning methods for Large-Scale Equivalence Checking and Function Correction
Authors
	Antiufeev G.V.
	Zhukov V.V.
	Zenin E.Y.
	Shupletsov M.S.
Date of publication
	2016
Abstract
	Efficient equivalence checking and functional correction on large-scale designs are crucial technologies for handling today’s demanding design cycles. It is well known that partitioning the design, based on two designs’ correspondence, can significantly reduce the complexity of the analysis. In the international contest «2015 CAD Contest at ICCAD» held within the scope of International Conference on Computer-Aided Designs 2015 (ICCAD) the research in the area of partitioning large designs into corresponding smaller designs that are easier to analyze was inspired. Contestants were challenged to insert cut points on large designs in an effort to reduce their equivalence checking and function correction problems. Equivalence checking (EC) and functional correction (ECO) are both used to analyze the Boolean difference between design specification and its logic implementation. For two processes (solving EC and ECO) the focus was on isolating large designs into corresponding smaller instances but with two different objectives. EC divides the large instances into smaller equivalent ones and cannot tolerate any non-equivalent sub-instances. ECO isolates the large instance into root-cause of changes and minimizes the non-equivalent sub-instance. Having effective circuit’s partitioning methods gives the possibility to address both the equivalence checking and functional correction problems in practice. In this paper the authors describe an approach of design partitioning that took the first place in the «2015 CAD Contest at ICCAD» contest. Furthermore different modifications are presented, which significantly improve the overall quality of the present approach.
Keywords
	Boolean circuits, logic synthesis, partitioning, equivalence checking, function correction, engineering change order, Boolean matching.
Library reference
	Antiufeev G.V., Zhukov V.V., Zenin E.Y., Shupletsov M.S. Partitioning methods for Large-Scale Equivalence Checking and Function Correction // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 1. P. 16-23.
URL of paper
	http://www.mes-conference.ru/data/year2016/pdf/D161.pdf