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Design of digital CMOS circuits for extreme temperatures |
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Authors |
| Vlasov A.O. |
| Marakhovsky V.B. |
| Surkov A.V. |
Date of publication |
| 2016 |
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Abstract |
| The article concerns the complexity of digital circuits design for extended temperature ranges. TSMC 65GP process was used in research. We developed physical layouts of three different implementations of 8-bit integer Fused Multiply-Add (FMA) circuit: synchronous, self-timed and self-timed with partial acknowledgement. GALA approach and early developed approach of direct translation of synchronous pipeline into self-timed one were used in design of both self-timed circuits.
Comparative analysis in typical corner was made on the results of three different approaches, i.e. spice (Cadence Spectre) simulations, time- and power- estimation in Cadence Encounter, and functional simulations with delays. All three approaches reveal matching results within 5-10% deviation.
Spice simulations of three implementations of FMA under condition of 1V supply and temperature variations from -175°Ñ till +200°Ñ show us the lack of performance and higher consumption of self-timed implementation in comparison with synchronous one. Disadvantages of synchronous approach are lack in performance with temperature range expansion and unpredictable behavior of circuit, designed using existing transistor models (which are intended to use within -40°Ñ .. +125°Ñ range). In addition we provide simulations of both self-timed circuits under condition of +25°C temperature and supply variations from 200mV till 1.2V. Simulation results show operability of self-timed circuits with under-threshold voltage supply. The self-timed circuit with partial acknowledgement shows the better performance and lower consumption than the self-timed circuit with full acknowledgement. |
Keywords |
| extreme environments, self-timed circuits, GALA, EDA. |
Library reference |
| Vlasov A.O., Marakhovsky V.B., Surkov A.V. Design of digital CMOS circuits for extreme temperatures // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 4. P. 51-58. |
URL of paper |
| http://www.mes-conference.ru/data/year2016/pdf/D162.pdf |
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