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Integrated S-band 6-bit Vector-Sum Phase Shifter with Decreased Phase Error
Authors
	Balashov E.V.
	Korotkov A.S.
	Rumiantsev I.A.
Date of publication
	2016
Abstract
	Active phased array antennas are widely used in radiolocation and telecommunication systems and consist of hundreds and thousands transceiver modules. Each module includes a phase shifter as a key element. The phase shifter is used to change the input signal phase depending on the control signal. There are different phase shifter types [1]: reflective, distributed, switched [6], vector-sum. Many papers about vector-sum phase shifters have been published during last years [2-4]. This paper presents the vector-sum phase shifter with calibration process after production to improve its characteristics. The S-band transformerless vector-sum phase shifter with decreased phase error is designed in 0.18 um CMOS technology. To decrease the phase error two special techniques are used: an unbalanced transformerless architecture and a post-silicon calibration. Commonly, the vector-sum phase shifter includes an input transformer, a polyphase filter and variable gain amplifiers. The input unbalanced signal is transformed into the differential form by the input balun. Then two differential orthogonal signals are obtained from the differential signal using the polyphase filter. Finally, two orthogonal signals are combined with different amplitudes. The amplitudes depend on the digital control signal. The input on-chip balun and process parameters variation introduce the phase error. To decrease the phase shifter error the designed vector-sum phase shifter is based on the unbalanced transformerless architecture [5]. In this architecture the RC-polyphase filter with single-ended input and differential variable gain amplifiers form the weighted quadrature signals. To eliminate the influence of the process parameters variation a post-silicon calibration is prosed. The phase shifter consists of the four main blocks: a high frequency analog block, a digital-to-analog block, a digital control block and a bias current generator block. The high frequency analog block is used for transformations of the input signal and implements the unbalanced transformerless vector-sum phase shifter architecture. The digital-to-analog block consists of two digital-to-analog converters: main and calibration. The digital control block is used for converting input 6 bit digital signal to the signals that control the switches in the digital-to-analog block. Other functions of the digital control block are calibration and storing of the calibration coefficients. The bias current generator block consists of a reference current source and an array of current mirrors to supply each block of the phase shifter with appropriate bias current. The designed 6-bit vector-sum phase shifter is fabricated in 0.18 um CMOS process. Total chip area is 5.3 sq. mm. The circuit area excluding electrostatic discharge protection ring is about 3.3 sq. mm. The phase shifter has maximum gain of 3.2 dB in 2.8 – 3.2 GHz frequency range with 0.4 dB variation. The maximum phase error and the root-mean-square phase error are less than 1.5 degree and 1.0 degree respectively. Total current consumption is about 55 mA from a 1.8 V supply voltage.
Keywords
	vector-sum phase shifter, calibration, CMOS technology.
Library reference
	Balashov E.V., Korotkov A.S., Rumiantsev I.A. Integrated S-band 6-bit Vector-Sum Phase Shifter with Decreased Phase Error // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 3. P. 39-44.
URL of paper
	http://www.mes-conference.ru/data/year2016/pdf/D153.pdf