Features of experimental research methods for memory with error correction

Boruzdina, A.B.; Temirbulatov, M.S.; Pechenkin, A.A.; Ulanova, A.V.; Yashanin, I.B.; Enns, V.I.; Yanenko, A.V.; Chumakov, A.I.

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Features of experimental research methods for memory with error correction

Authors

Date of publication

2016

Abstract

On-chip error correction is a widely used technique for SRAM SEU-hardening [1-3]. Application of error correction allows a designer to use a commercial 6T-cell for SRAM blocks, which results in substantially smaller die sizes, compared to a device implementing hardened 10T-cell, without significant increase of SEU-sensitivity
The paper presents results of experimental study of SEU-hardness of SRAM with error correction for turned on and turned off correction circuits. The validity of analytical model [4, 5] was investigated based on combined evaluations obtained during tests performed at ion and proton accelerators and focused laser sources.

Keywords

Multiple Bit Upset (MBU), Multiple Cell Upset (MCU), SRAM, error-correcting codes.

Library reference

Boruzdina A.B., Temirbulatov M.S., Pechenkin A.A., Ulanova A.V., Yashanin I.B., Enns V.I., Yanenko A.V., Chumakov A.I. Features of experimental research methods for memory with error correction // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 4. P. 184-189.

URL of paper

http://www.mes-conference.ru/data/year2016/pdf/D141.pdf