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SD Host Controller IP-core
Authors
	Rutkevich A.V.
	Khaylo N.N.
	Sysoev I.Y.
Date of publication
	2016
Abstract
	The purpose of this thesis work was to design and implement an AMBA compatible SD Host controller for an ASIC and FPGA implementation. The SD Host Controller handles SD Protocol at transmission level, packing data, adding CRC, Start/End bit, and checking for transaction format correctness. The Host Controller provides Programmed IO method and DMA data transfer method. In programmed IO method, the Host processor transfers data using the Buffer Data Port Register. The host interface is based on a standard 32-bit Advanced Peripheral Bus (APB), which is used to configure the IP, and Advanced High-Performance Bus (AHB), which is used to transfer data. SD Host Controller IP features: • Compliant to SD Physical Layer Specifications version 4.00; • Supports SDR12, SDR25, SDR50, DDR50 modes of operation; • Support up to 50 MBps speed; • Supports 1/4-bit data transfer; • Cyclic Redundancy Check (CRC): CRC7 for commands, CRC16 for data integrity; • Variable-length data transfer; • Card Detection (Insertion/Removal); • In-built clock divider; • Supports ADMA2 mode of data transfer; • Supports interrupts; • Supports 32-bit AMBA APB slave interface for register configuration; • Supports 32-bit AMBA AHB master interface for data transfer. FPGA (Kintex-7 XC7K325T-2FFG900) implementation: • flip-flop count: 18750 (4,6 %); • LUT count: 9052 (4,4 %); • slices count: 25828 (6,3 %). ASIC (180 nm) implementation area: 2.86 mm2.
Keywords
	IP-core, SD, SD Host, AMBA, ASIC, system-on-a-chip, SoC.
Library reference
	Rutkevich A.V., Khaylo N.N., Sysoev I.Y. SD Host Controller IP-core // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 3. P. 191-197.
URL of paper
	http://www.mes-conference.ru/data/year2016/pdf/D140.pdf