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28nm IC’s Parameters Optimization without RTL Changing
Authors
	Vlasov A.O.
Date of publication
	2016
Abstract
	In 28nm technology designs static power of leakage currents is as critical as time performance. The most effective means of reducing this effect is to disable the power supplies in inactive blocks. However, this approach requires a change in a project RTL and additional efforts at all stages of design flow. This article describes the approaches based on the selection of the most appropriate for a particular project set of technology libraries, the next using of their elements in the design and the setting parameters of EDA. These methods have one very important advantage: all processes optimization have become the original flow phases of design and don’t depend on the input logic RTL-description circuit. This article, using as the example, the microprocessor KOMDIV64 series core cpu, shows the approaches to implement: 1) Selection of standard cell libraries for design optimization. The influence of options TSMC 28HPC 7-track library on the parameters static power and performance was studied. The static power and speed of implementations, based on LVT, RVT, HVT and the multi length option libraries, were compared 2) Optimization of the project using several standard cell libraries. The use of several libraries in a design flow allows "strong" side of one of the libraries "weak" may neutralize other. Several ways of such optimization were analyzed 3) Selection the memory parameters to achieve design goals. LVT, RVT, HVT memories variants were compared using the static power and speed 4) The effective using of the selected set of library elements to achieve the best compromise between power of leakage currents and time performance of microprocessor core cpu The set of library data which was found as the optimal one let reduce more than 7 times the static power of leakage currents with the loss of productivity by 16%.
Keywords
	TSMC 28HPC, synthesis, standard cell libraries, memory compilers, leakage current power reduction, performance optimization.
Library reference
	Vlasov A.O. 28nm IC’s Parameters Optimization without RTL Changing // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 1. P. 64-69.
URL of paper
	http://www.mes-conference.ru/data/year2016/pdf/D110.pdf