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IP-Core SD Device Development
Authors
	Voronkov D.I.
	Veykov A.A.
	Sysoev I.Y.
Date of publication
	2016
Abstract
	In this work IP Core SD Device development are described. IP Core has been developed for 0.18 um rad-tolerant CMOS library. IP Core uses 2,3 um2 on chip. Max speed 50 Mbyte/s. IP Core support Default Speed (DS), High Speed (HS), SDR12 (single data rate, 12 Mbyte/s), SDR25 (25 Mbyte/s), SDR50 (50 Mbyte/s), DDR50 (double data rate, 50 Mbyte/s). IP Core frequency are equal 100 MHz. Also SD Device has been developed for FPGA Kintex-7 (XC7K325T-2FFG900) with following requirements: 2% of flip-flops, 13% of LUTs, 14% of slices. For CPU and DMA connection IP Core has AMBA APB and AMBA AHB accordingly.
Keywords
	IP-core, Secure Digital, SD, DDR, AMBA, SoC, ASIC.
Library reference
	Voronkov D.I., Veykov A.A., Sysoev I.Y. IP-Core SD Device Development // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 3. P. 186-190.
URL of paper
	http://www.mes-conference.ru/data/year2016/pdf/D105.pdf