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Routing of Memory Bits Cells with Automated Construction of Boundary Layout Constraints
Authors
	Ryzhenko N.V.
	Bykov S.A.
	Sorokin A.A.
Date of publication
	2016
Abstract
	In this paper we present a solution for the automatic routing of memory bit array cells. The memory consists of two main parts. Bit arrays store the information. Peripheral logic controls reading and writing to the memory. Peripheral logic can be constructed of standard cells. Memory arrays are constructed of a specially designed memory bit cells. Memory cell design opposes to the standard cell methodology where each cell must be legal to any other cell from the library for all possible allowed mutual placements. Bit cells can share layout, for example adjacent cells can share diffusions. Usually it’s power and ground nets. Diffusion sharing of adjacent bit cells allows to achieve ultimate transistor density. And memory cells don’t have pins in traditional meaning. All nets are either power, ground, internal or connected to buses. Straight buses come across the whole memory array. There are two technology trends in the industry. While the optical lithography wave length 193nm remains unchanged, feature size continues to scale down according to the Moor’s low. The complexity and the number of design rules constantly grow [1]-[2]. Another trend is that layout becomes more and more regular [3]. Limited number of patterns in regular layouts reduces the complexity of the optical proximity correction. Also regular layouts make easier formulation of particular design rules. Regular layout allows to use efficient data models [6]. While layouts objects are complete discrete and gridded the data model codes with uncompromised accuracy all possible design rules. Regular layouts and recent dramatic improvements in the solvers make possible the use of the Boolean Satisfiability (SAT) for the standard cell routing [4]-[5]. Key features of the SAT routing is completeness. SAT solver either finds a legal DR-clean solution or reports that such solution doesn’t exist under constraints. Design and development of memory bit cells is traditionally done manually because is cost-effective. Any VLSI utilizes very few types of memory, so that very few types of memory bit cells. At the same time there’re maybe hundred thousand or millions of instances of identical bit cells in the design. That’s why every bit cell is designed to be super optimal in terms of transistor density, power and performance. Challenges of modern nanometer technologies make manual design of bit cells unpractical. We propose to extend algorithms of the standard cell routing [4]-[5] for the memory bit cells. A proposal is to place bit cells in a small block. The variety of borders between adjacent cells in this block must model all possible borders between cells in a real-size memory array. One of cells in the block is marked as master, other cells are marked as children. We impose an additional constraint that if the master has a piece of layout at some point every child must have same piece of layout at the same point. If the master has an empty space at some point then every child must have same empty space at the same point. These extra constraints are translated into the common SAT formula and after the SAT routing master and children get identical layout and master cell is legal to all cells around. Another modification is that adjacent cells share busses as same nets. Basically the rest of the routing algorithm remains unchanged. A block of cells is routed as a big flat super-cell. Experimental results demonstrated applicability of the proposed approach for routing industrial types of bit cells [9]. The algorithm was used to route real bit cells.
Keywords
	routing, memory, standard cells, design rules, Boolean satisfiability.
Library reference
	Ryzhenko N.V., Bykov S.A., Sorokin A.A. Routing of Memory Bits Cells with Automated Construction of Boundary Layout Constraints // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 1. P. 144-150.
URL of paper
	http://www.mes-conference.ru/data/year2016/pdf/D103.pdf