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Cognitive Contradiction’s Visualization for VLSI Layout Decomposition for Double Patterning Issues
Authors
	Verstov V.A.
	Zinchenko L.A.
	Makarchuk V.V.
	Shakhnov V.A.
Date of publication
	2016
Abstract
	In the paper, we discuss cognitive techniques for contradiction visualization during VLSI layout decomposition for double patterning. Our goal is visual analytics support of time-consuming VLSI design process. Larger datasets, including information about contradictions between polygons, are generated during VLSI layout decomposition for double patterning. Contradiction graph that is one of results of layout decomposition attempt consists of billions of vertices and edges. Vertices represent polygons. Edges represent contradictions. Analysis of contradictions’ data and the new VLSI layout is a complex task for a VLSI design engineer because links between the cell hierarchy and the contradiction graph are missed. To overcome this deficiency, we propose a special visual model that simplifies problematic layout parts localization. Our analytics are based on graph models for VLSI layout representation. We propose contradiction classification. Our classification helps to manage data during VLSI SOI layout design. We illustrate our approach for contradictions visualization for double patterning technology case study. We change vertices radius depending of contradictions types and its amount. Proposed cognitive approach for contradiction management during VLSI layout decomposition for multiple patterning could reduce design efforts. All case studies are generated by Parallel DPLayout Migrator software. The proposed cognitive approach makes the user-machine interface of Parallel DPLayout Migrator easier. The proposed visualization techniques support design process and add cognitive elements in layout EDA tools. The reported research study was partially funded by RFBR according to the research project No. 16-37-00254 mol_a.
Keywords
	cognitive informatics, visualization, VLSI, EDA, graph theory, double patterning.
Library reference
	Verstov V.A., Zinchenko L.A., Makarchuk V.V., Shakhnov V.A. Cognitive Contradiction’s Visualization for VLSI Layout Decomposition for Double Patterning Issues // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 1. P. 158-164.
URL of paper
	http://www.mes-conference.ru/data/year2016/pdf/D100.pdf