Automation of verification environments development process providing a through design flow for design, verification and research of IP-blocks and SoC

Zhezlov, K.A.; Kolbasov, Y.S.; Kozlov, A.O.; Nikolaev, A.V.; Putrya, F.M.; Frolova, S.E.

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Automation of verification environments development process providing a through design flow for design, verification and research of IP-blocks and SoC

Authors

Date of publication

2016

Abstract

The article pays main attention to the automation of the process of infrastructure creation for functional verification of IP blocks, first of all verification environments, compile tools and test results analysis. The attention is also paid to estimating efficiency of a block or system performance. A distinctive feature of the infrastructure being developed is portability of tests and a high degree of reuse of environment components, such as tools for comilation of tests, verification environments and test results analysis.
Automated process of creating a verification infrastructure accelerated and simplified the process of creating environments for IP blocks. Tests for standalone environments could be run on the system environments. Standardization of verification environments output information makes a single infrastructure for the study of the test results and characteristics of IP blocks.
The authors describe how to ensure the rapid creation of a test harness for the system-level environments based on the use of debugged code of standalone environments
It is showed that the accumulated code of test programs and drivers is easily portable between the verification steps and can be used as a reference for the development of software for the serial IC designs
The modular tool for automation of design flow for creation and verification of SoC and a system of releases allow to standardize the interaction of groups of verificators and developers, which affected the duration of projects. Also that tool allowed to formalize and automate many stages of the design and verification of system-on-chip.

Keywords

SoC, verification, verification environments, generation, standardization, parametric control.

Library reference

Zhezlov K.A., Kolbasov Y.S., Kozlov A.O., Nikolaev A.V., Putrya F.M., Frolova S.E. Automation of verification environments development process providing a through design flow for design, verification and research of IP-blocks and SoC // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 2. P. 46-53.

URL of paper

http://www.mes-conference.ru/data/year2016/pdf/D094.pdf