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The technique of logical circuit parameters selection in nanometer RHBD CMOS VLSI
Authors
	Gerasimov Yu.M.
	Grigoryev N.G.
	Kobylyatskiy A.V.
Date of publication
	2016
Abstract
	One of the main problems in the transition to smaller design rules becomes higher sensitivity to the outer space heavy particles of the logic elements [1]. Modern radiation-hardened-by-design "system-on-chips" are equipped with internal error correction (EDAC) systems that can effectively detect and correct single event effects in SRAMs [2]. However, the effects of single particle strikes may also occur in the flip-flops and latches in synchronization tracts and control logic. Such types of errors cannot be corrected. The effects from heavy particles strikes at logical circuits result in single voltage pulses (Single Event Transient, SET). The most critical to SET elements are the most high-speed chains – clocking and synchronization circuits. Undesirable voltage pulses that penetrate deep into scheme, can cause malfunctions. Therefore, during the design of synchronization circuits in nanometer RHBD VLSI it is necessary to apply additional methods to improve their heavy particles tolerance. Most of the existing methods of radiation-hardening-by-design at the system and circuit levels are intended to limit the spread and penetration ways of undesired voltage pulses deep into the logical hierarchy [3]. The most common methods are: hardware and temporal doubling and triple redundancy, majority and clocked logic. The application of such methods allows effectively neutralizes the consequences caused by SET, but do not deals with the reasons. The best way to eliminate the reasons of SET initiation is the sizing of the transistors [4]. Generally, in the articles dealing with the design of logical circuits that are tolerant to heavy ions, the sizes of transistors are not theoretically justified. Nowadays, the theoretical aspects of SET occurrence in the logic circuit are discussed in detail in [4] - [5]. There are presented the mathematical models designed for the SET calculations in the SPICE simulators. They also allow to achieve highly accurate results. However, during the analysis of technical specifications and the preliminary estimation of the electrical parameters and circuit area such accuracy is not required. In these articles also analyzes the impact of the total node capacitance at the amplitude characteristics of the SPE. This article presents the technique of selecting optimal parameters for a given level of logical circuit radiation hardness based on a simple mathematical model of the SET. The technique is considered by the example of a simple logic circuit. It is invariant to the technological basis and also allows to reach a compromise on the main electrical parameters. During the research the detailed analysis of various parameters and their impact on the logical circuit critical charge of the SET occurrence was held. Some recommendations for the logical circuits design with a large fan-out ratio are given. It is shown that the low power factor of an element can let to the huge amount of the critical charge because of the open transistor current value.
Keywords
	logic circuit, invertor, CMOS VLSI, heavy particles, single event effects, RHBD.
Library reference
	Gerasimov Yu.M., Grigoryev N.G., Kobylyatskiy A.V. The technique of logical circuit parameters selection in nanometer RHBD CMOS VLSI // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 4. P. 172-177.
URL of paper
	http://www.mes-conference.ru/data/year2016/pdf/D087.pdf