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Reliability evaluation for SEU in cache in system-on-chip design
Authors
	Mamoutova O.V.
Date of publication
	2016
Abstract
	Systems-on-chip are widely used in modern spacecrafts to meet the increasing data processing requirements. With the current level of technology systems-on-chip are highly susceptible to soft errors. The proper choice of measures to improve the reliability should be based on reliability evaluations at every design stage. Modern methodologies of design for reliability still lack a full set of the necessary methods though. This work examines the reliability estimation problem for a cache memory as the most vulnerable node of a system-on-chip. The paper reviews the state-of-the-art analysis methods and presents new methods, which are suitable for the de-facto standard platform-based design approach. The first method is a fully analytical evaluation of a cache vulnerability to soft errors. The method gives insight into relationships between parameters of the reliability function and allows fast rough reliability estimations at the early design stages. The second method supports emulated fault injection experiments by instrumentation of a cache memory with saboteurs, which are controlled by the processor of the tested system itself. This method reduces both chip area overheads and estimation time. The presented methods assist in the process of design space exploration for a platform-based design methodology. Fast analytical evaluations of reliability are necessary during the system level design to select the platform parameters. Then a selected solution is synthesized and verified using FPGA, when emulated fault injection is necessary. Then obtained vulnerability factors complement the interpretation of results after physical radiation tests. The presented case study for a data cache of a small satellite’s on-board computer illustrates this design flow.
Keywords
	System-on-chip, SoC, platform, cache, memory, reliability, SEU, soft error, simulation, fault injection.
Library reference
	Mamoutova O.V. Reliability evaluation for SEU in cache in system-on-chip design // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 4. P. 166-171.
URL of paper
	http://www.mes-conference.ru/data/year2016/pdf/D073.pdf