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Analysis of the impact of standard cells placement and power network configuration on the layout design of a microprocessor component
Authors
	Lobanova A.Y.
	Menshenin L.V.
Date of publication
	2016
Abstract
	Physical designers of microprocessors constantly try to obtain improved parameters of the chip power grid. In layout they try to reduce resistive voltage drop and minimize the probability of the electromigration. Otherwise, the intended operation of the chip could be broken. This is complicated by the need to ensure the sufficient amount of the routing. In this paper, the customized methods of standard cell placement and power grid configuration are described on the example of the layout design of ARINC-429 interface controller block. These methods are aimed on preservation of the sufficient routing resources while minimizing IR-drop and electromigration risk. Four variants of the standard cells placement inside of block were considered. Evenly distributed logic cells and clock tree buffers resulted in the best layout parameters by the comparison. It was also considered four configurations of power grid on 6-metal technology. They all took the same amount of metal and trace resources. The analysis of the obtained data showed the best configuration for use in the complex-function microprocessor’s blocks like massively parallel computation. The electromigration risk, voltage drop, routing resources and decoupling capacitance of the power grid are analyzed for all mentioned cases.
Keywords
	Power grid, IR voltage drop, electromigration reliability.
Library reference
	Lobanova A.Y., Menshenin L.V. Analysis of the impact of standard cells placement and power network configuration on the layout design of a microprocessor component // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 1. P. 179-186.
URL of paper
	http://www.mes-conference.ru/data/year2016/pdf/D068.pdf