The methodology of the automated generation and analysis of basic structures for the design of dynamic and static protection the blocks of integrated circuits against ESD

Ilin, S.A.; Kochanov, S.K.; Lastochkin, O.V.; Novikov, A.A.

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The methodology of the automated generation and analysis of basic structures for the design of dynamic and static protection the blocks of integrated circuits against ESD

Authors

Date of publication

2016

Abstract

The article describes a methodology of dynamic and static IC protection blocks designing against electrostatic discharge (ESD). The methodology is based on the automated generation of schematic representations and analyzing their electrical parameters based on the selected criteria.
The development of semiconductor technology is accompanied by a constant decline in the depth of the p-n junctions, a decrease in the gate oxide thickness and the interconnect lines thickness, which increases the likelihood of damage to ICs from ESD.
A relatively new challenge for the developers becomes the migration of finished and passed successfully tested security solutions against ESR for more modern semiconductor technology.
Semiconductor factories provide developers with a wide range of basic components to build blocks of ESD protection: various types of diodes, specialized transistors, SCR-structure.
In the considered architecture the static protection circuits are part of input-output cells, dynamic protection circuit is included in the Clamp elements. Dynamic protection circuit is a complex device for detection of stress, activation element of high conductivity and redistribution of peak current. Elements of static protection are usually designed on the basis of the diode pair. Dynamic protection circuit is designed based on a transistor (or transistors distributed array) with RC-circuit elements and control circuitry. The area occupied by elements of the static and dynamic protection with respect to the square characteristic of the selected IO cell technology is great enough.
To reduce the time and improve the efficiency of protection components design, the methodology of the automated generation of the basic constructs with the desired electrical parameters and satisfying the given constraints is presented. Taking into account the large number of constraints, variable basic elements, developed protection circuit parameters and requirements for the scheme functioning conditions, the effectiveness of its development can be greatly improved by automatization of this phase. The proposed methodology is based on the joint use of specialized software package and the route of design. The effectiveness evaluation of each structural element is based on circuit simulation. The developed software allows to automatically create and analyze accordingly a given algorithm the unlimited number of constructs variants, and provides a search that most closely matches the specified criteria and options parameters. The result of the software work is a database (DB) of the basic constructs for static and dynamic protection circuits. From the resulting database in an automatic mode, the selection is carried out satisfying the specified criteria constructs.
When designing an ESD protection circuit has the following problems:
- A high degree of variability of the main parameters of the basic constructs;
- A large number of species of elements (diodes, transistors), increasing with each new technology;
- The variety of circuit solutions and their combinations;
- Complexity of determining the most suitable solutions to achieve the desired resistance value the impact of ESR in a reasonable time.
To solve the problems, it is proposed to use specialized software that implements:
- Automatic generation of the test constructs, and combinations thereof;
- The formation of the test environment and the generation of input actions;
- Calculation of the constructs parameters based on circuit simulation;
- Analysis of the results.
To test the effectiveness of a methodology as a starting point were selected input-output cells from the library, created on the basis of Mikron SOI technology 250nm.
Of interest for static protection circuit is a diode structure that can hold the specified current (up to 15A), corresponding to a particular value of ESR. To improve reliability, preference may be given construct, reached the lowest voltage value, but it will be different this constructive increased geometric dimensions.
The same requirements and algorithm of actions apply for transistors construct of dynamic protection circuit. In the experiment using the proposed methodology was able to override parameters of the initial basic constructs. Since the area occupied by one diodes pair designed for ESR current - 2A, and defined by the methodology procedure decreased 5-fold compared to the original one, and the Clamp-transistor calculated for 2A was able to reduce to about 4 times.
Due to the high variability of constructs and, as a consequence, a significant number of options for the structures and its electrical parameters, there is a need to formulate criteria for sorting and selecting the most fully satisfying the specified conditions of constructs.
The first criteria for static protection schemes sorting is the current capacity of the security element, or the maximum current is passed, withstand construct. Each ESD type has its own stress current. Although the same bandwidth the constructs can significantly differ from each other as the occupied area, and shape. The second criterion relates to the geometric sorting. The diode on the width should not exceed the width the contact area. This helps significantly to reduce the number of these elements. Another important point is the ability to limit the height of the resulting constructs. Thus, it becomes possible to reduce the amount of suitable basic constructs another 30%. The third criteria is sorted by diode voltage drop. This criteria is only available for constructs diodes since their characteristics analysis. Reducing the number of diode does not occur, but the elements that have the required bandwidth are at a lower voltage drop at the top of the database table, as the most suitable for use.
The first criteria for dynamic protection schemes sorting is the current response time, or rather switch on delay dynamic protection circuit. This criteria helps to find the fastest circuit and sort the results by ascending delay. In addition to activation rate important parameter is the duration of the CLAMP-cells throughout the stress exposure. The second criteria is the selection for the front rise time and current cutoff response in relation to the rise time and input voltage cutoff. Despite the importance of the dynamic protection schemes timing, footprint remains a major.
So the static protection circuit as the most important criteria are selected for the current throughput capacity, footprint and the voltage drop. For dynamic protection circuit are selected on criteria of circuit response delay, the time of work during the whole of stress, current throughput capabilities and footprint.
Integration defined criteria in the developed software has reduced the scope of analysis for static protection circuits from 60 thousand of the obtained configuration to ~ 800. For dynamic protection circuit analysis scope was reduced from ~ 85 000 the obtained results up to 450 configurations that allows for a more detailed analysis by the developer.
The proposed methodology and software technologically independent, that enables their use in the development of IC protection circuits against ESD and IO libraries for all the family of technologies CMOS/SOI 250/180/90/65nm and below. They can be used for the correction of existing solutions by changes in technology or engineering tools, for example, such as changes in Spice-models or PDK, through migration of IO cells, between the options one technology or different technologies.
The proposed methodology has been tested and shown to be effective in the development and initial evaluation constructs ESD protection for the IO elements libraries on domestic technology SOI 250/180 nm.

Keywords

dynamic protection circuit against ESD, static protection circuit against ESD, automated generation of schematic representations, designing the route, specialized software.

Library reference

Ilin S.A., Kochanov S.K., Lastochkin O.V., Novikov A.A. The methodology of the automated generation and analysis of basic structures for the design of dynamic and static protection the blocks of integrated circuits against ESD // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 3. P. 100-105.

URL of paper

http://www.mes-conference.ru/data/year2016/pdf/D053.pdf