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Route of development and FPGA-verifications of IP-core of controller SpaseWire link for "system-on-chip" on the basis of platform "MultiCore"
Authors
	Shejnin Yu.E.
	Suvorova E.A.
	Rozhdestvenskij D.A.
	Solokhina T.V.
	Glushkov A.V.
	Alekseev I.N.
	Gerasimov Yu.M.
Date of publication
	2005
Abstract
	In the report the review of a full route of designing and verification of IP-kernel on an example of the controller of link Spacewire for “system-on-chip” (SoC) on the basis of platform "MultiCore" is presented.
Keywords
	FPGA, system-on-chip, platform "MultiCore"
Library reference
	Shejnin Yu.E., Suvorova E.A., Rozhdestvenskij D.A., Solokhina T.V., Glushkov A.V., Alekseev I.N., Gerasimov Yu.M. Route of development and FPGA-verifications of IP-core of controller SpaseWire link for "system-on-chip" on the basis of platform "MultiCore" // Problems of Perspective Microelectronic Systems Development - 2005. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2005. P. 484-486.
URL of paper
	http://www.mes-conference.ru/data/year2005/72.doc