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Computer memory subsystem optimization by providing guaranteed memory bandwidth
Authors
	Kornilenko A.V.
	Esula O.I.
Date of publication
	2016
Abstract
	In modern microprocessors [1] a memory controller receives requests to write or read from a number of system components (microprocessor core, SATA, USB, Ethernet controllers and other peripheral devices). Arbitration challenge has well known decisions [2], that depend on technical requirements. The article describes the various algorithms of memory requests arbitration, which were implemented in processors 1890VM5, 1890VM6, 1890VM8 and 1890VM9. Each memory controller of the given processors has its own arbiter for ordering requests from different devices. But scheduling algorithms in different processors are different. 1890VM5 has a few components, only three, so it was enough to use fixed priority algorithm for arbitration. 1890VM6 has seven system components. Round-Robin [3] algorithm was used to guarantee access to the memory for all the devices and to provide required performance [4]. In 1890VM8 the number of system components increased, but the memory channels number wasn’t changed. There is additional commutator level of arbitration with Round-Robin algorithm before the request reaches the memory controller. In the memory controller Least Recently Used (LRU) [5] is used. This algorithm does not require a long RTL simulation for verification [6], it takes tests several hours to pass. The arbitration algorithms, used in previous versions of memory controllers do not provide the necessary level of quality of service (QoS) [7] for all required modes for 1890VM9. So algorithm LRU was complicated. Each channel of the memory controller was assigned a number to indicate the number of requests that have a constant priority. We analyzed the dependence the relative bandwidth of the memory channel of this assigned number. Based on the results of the analysis for the processor 1890VM9 four bits for the number is used, which encode 16 values. Thus, dynamic switching allows us to change the bandwidth of the memory channel based on the tasks in the process. We evaluated the efficiency the arbitration algorithms of the given projects. Thus, it is evident that LRU with the mechanism of providing guaranteed bandwidth has the advantage over other used algorithms. This algorithm allows to configure the time of data waiting for the memory channel in accordance with the technical requirements and task conditions. The effectiveness of the arbitration algorithms used in processors 1890VM5, 1890VM6, 1890VM8 and 1890VM9 confirmed by the results of performance tests (LMbench [8]).
Keywords
	system-on-a-chip, SoC, QoS, memory subsystem.
Library reference
	Kornilenko A.V., Esula O.I. Computer memory subsystem optimization by providing guaranteed memory bandwidth // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 3. P. 136-140.
URL of paper
	http://www.mes-conference.ru/data/year2016/pdf/D020.pdf