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The methods of time-logic analysis of library elements and VLSI blocks for advanced technologies with a vertical transistor’s gate
Authors
	Gavrilov S.V.
	Zhukova T.D.
	Ryzhova D.I.
Date of publication
	2016
Abstract
	With the reduction of standard elements size, the degradation of transistors electrical parameters grows dramatically as the negative impact of the short-channel effects is increased. This results in the need to develop alternative technological solutions which scaled better than existing solutions and compatible with CMOS manufacturing process. One of the most promising solution in this field is the CMOS technology with 3D transistor’s gate. In the foreign literature FinFET term is used (Fin Field Effect Transistor – field effect transistor with 3D structure in the shape of fin). The advantages of this technology are low sensitivity to the short-channel effects and low subthreshold leakage. Today CAD tools for layout synthesis for circuits based on FinFET structures are absent, since for 22 nm technologies and below the number of design rules and constrains is significantly increased. In this paper we attempt to solve the problem of increasing number of design rules by using regular structures in layout layers.
Keywords
	CAD (computer-aided design), SP-DAG, Intellective property (IP-block), FinFET transistor, CMOS technology.
Library reference
	Gavrilov S.V., Zhukova T.D., Ryzhova D.I. The methods of time-logic analysis of library elements and VLSI blocks for advanced technologies with a vertical transistor’s gate // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 1. P. 56-63.
URL of paper
	http://www.mes-conference.ru/data/year2016/pdf/D006.pdf