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The use of VHDL models of partial Boolean functions for the design of digital circuits
Authors
	Bibilo P.N.
Date of publication
	2016
Abstract
	Modern synthesizers perform high-level synthesis of logical circuits by a compiled method – each construction of original VHDL-description is replaced by the description of corresponding logical subcircuits [1]. The results of synthesis depend substantially on the original VHDL description which is given to the input of the synthesizer. In this work, methods for description of incompletely specified (partial) Boolean functions in VHDL systems are proposed. During the synthesis process, original VHDL descriptions turn into combinational logic circuits whose behavior models are systems of completely specified functions. It is known in the literature, the use of don’t care values of Boolean functions in the synthesis of logical circuits may result in more economy circuits [2]. Examples of synthesized VHDL models of partial Boolean functions are presented; and the results of experiments on circuit implementation of VHDL descriptions of systems of partial functions. The realizability of original partial functions in logical circuits was verified by formal verification [6]. The main optimization directions of descriptions of systems of partial Boolean functions are minimization in DNF class, optimization multi-level representations based on Shannon’s expansion (BDD-optimization) [4, 5] and decomposition [6, 7]. Theoretical methods on above optimization directions are studied in the literature quite well [2, 3]. The influence of methods for logical optimization on the results of logical synthesis in the design library of domestic VLSI custom circuits has been investigated by experiment in [3, 8] for systems of completely specified functions. The experiments with logical optimization programs on the flow of practical examples show that for various combinational circuits it is rational to use various optimization procedures (minimization in the DNF class, BDD-optimization, decomposition) [8]. However, BDD-optimization resulted more often in circuits requiring lesser area of the ASIC chip even comparing with the results of running the effective program ESPRESSO [9] for joint minimization in DNF class of systems of completely specified functions. We performed the experiments on circuit implementation of systems of partial Boolean functions in the ASIC design library [3] and with programmable logic integrated circuits Spartan 3-1000 of FPGA type. For joint minimization of partial functions in DNF class we used the program [10]. Using the facility of specification completion of partial functions for optimization allows reducing substantially the complexity of combinational logic circuits both in the case of designing circuit example of library elements and in the case of FPGA structures. Unlike the case of completely specified functions, joint minimization in DNF class of systems of partial functions in the experiments allowed to obtain better results in the synthesis compared to the optimization of BDD representations. The results of the experiments show that the preliminary minimization in DNF class and in the class of BDD representations for pseudo-random systems of completely specified functions does not improve practically (and in the case of BDD sometimes worsens) the results of the subsequent synthesis in the basis of FPGA unlike the significant efficiency of these procedures for the synthesis of benchmark circuits taken from the practice of the design [3, 6].
Keywords
	Boolean function, disjunctive normal form, binary decision diagram (BDD), synthesis of logical circuit, VHDL, FPGA
Library reference
	Bibilo P.N. The use of VHDL models of partial Boolean functions for the design of digital circuits // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 1. P. 2-8.
URL of paper
	http://www.mes-conference.ru/data/year2016/pdf/D004.pdf