| The architecture of scheduler of mapping processor of PDCS "Buran" |
|
|
| Authors |
| | Zmejev D.N. |
| | Levchenko N.N. |
| | Okunev A.S. |
| | Klimov A.V. |
| Date of publication |
| | 2014 |
|
| Abstract |
| | This article describes the hardware and software tools for scheduler of mapping processor of PDCS "Buran". Inclusion the scheduler into the computational core will allow effectively control the operation of the mapping processor by non-uniform loading of execution unit and prevent blocking of computation process on overflow of keys memory and other system hardware. |
| Keywords |
| | sheduler of mapping processor, dataflow computational model |
| Library reference |
| | Zmejev D.N., Levchenko N.N., Okunev A.S., Klimov A.V. The architecture of scheduler of mapping processor of PDCS "Buran" // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 4. P. 75-78. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2014/pdf/D156.pdf |
