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Testing and limiting metrological possibilities of pulse-potential ADC in SoC
Authors
	Krutchinsky S.G.
	Zhebrun E.A.
Date of publication
	2014
Abstract
	A testing procedure for the pulse-potential ADC, aimed at minimizing the influence of analog section zero drift on conversion accuracy of the input signal, is proposed. The procedure is based on the basic properties of the ADC - quantization of energy. It is shown that inserted testing phases, allowing to determine the binary words in common additive sequence of measured value, are correctional and not increasing its sensitivity. Parametric conditions for the method applicability, that justify the need of accessory circuitry tasks solution, are formulated.
Keywords
	Analog-to-digital converters, IP blocks testing, mixed systems-on-chip, zero drift, error of measurement.
Library reference
	Krutchinsky S.G., Zhebrun E.A. Testing and limiting metrological possibilities of pulse-potential ADC in SoC // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 3. P. 15-20.
URL of paper
	http://www.mes-conference.ru/data/year2014/pdf/D128.pdf