| The method of static power reducing for CMOS circuits based on sleep transistors with operation speed control |
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| Authors |
| | Volobuev P.S. |
| | Gavrilov S.V. |
| | Ryzhova D.I. |
| Date of publication |
| | 2014 |
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| Abstract |
| | Reduction of static power consumption is becoming a priority task in the design of integrated circuits based on the technology with design rules 90nm and below. Existing CAD tools provide low power consumption based on various circuit solutions, in particular applying sleep transistors. However, the existing data flow on the basis of library elements do not provide the required control of performance when using such circuit solutions. This article is devoted to solution of the operating speed control problems in the data flow of automated circuit solutions synthesis to reduce static power in the intellective property block (IP blocks) based on the power gating method. |
| Keywords |
| | intellective property block (IP block), static power consumption |
| Library reference |
| | Volobuev P.S., Gavrilov S.V., Ryzhova D.I. The method of static power reducing for CMOS circuits based on sleep transistors with operation speed control // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 1. P. 101-106. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2014/pdf/D121.pdf |
