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Variable-length code packing IP-core
Authors
	Belyaev I.A.
Date of publication
	2014
Abstract
	There are a lot of data compression algorithms that use variable-length coding (VLC) as last stage of compression. A variable-length code packing in fixed-length words is needed to form bitstream. Proposed IP-core perform packing of up to 32-bit length variable length codes into 32-bit fixed-length codewords. Advantage of proposed IP-core is set of program-invoked functions, that enhance working with memory efficiency and simplify bitstream forming process for SoC processor. The IP-core is implemented in RTL-model with SystemVerilog HDL. Hardware cost of the proposed IP-core is 7,8K gates with 40 nm technology and 2 ns (500 MHz) timing constrain.
Keywords
	IP-core, data compression, variable-length coding, VLC, packing, system-on-a-chip, SoC.
Library reference
	Belyaev I.A. Variable-length code packing IP-core // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 4. P. 25-28.
URL of paper
	http://www.mes-conference.ru/data/year2014/pdf/D095.pdf