| Initial placement of digital logic cells in integrated circuits considering net priority |
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| Authors |
| | Harutyunyan A.G. |
| Date of publication |
| | 2014 |
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| Abstract |
| | A method for initial placement of logic cells in integrated circuits (ICs) based on net delay is proposed. The method is based on the preliminary assessment of the timing characteristics of digital ICs and net delay budget. The obtained values of the delay budgets are then used for logic cells placement. |
| Keywords |
| | digital integrated circuit, path slack, critical path, initial placement |
| Library reference |
| | Harutyunyan A.G. Initial placement of digital logic cells in integrated circuits considering net priority // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 1. P. 143-146. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2014/pdf/D080.pdf |
