| Modern methods of functional verification RTL-models blocks for VLSI microprocessor |
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| Authors |
| | Barskikh M.E. |
| | Aryashev S.I. |
| | Rogatkin B.Yu. |
| Date of publication |
| | 2014 |
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| Abstract |
| | The article describes the technique of functional verification for RTL blocks of VLSI microprocessor, translation lookaside buffer (TLB) as example. In the framework of a widespread the universal verification methodology (UVM) this approach can be used to verify other RTL models of digital hardware. |
| Keywords |
| | functional verification, verification plan, test environment, UVM |
| Library reference |
| | Barskikh M.E., Aryashev S.I., Rogatkin B.Yu. Modern methods of functional verification RTL-models blocks for VLSI microprocessor // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 2. P. 119-122. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2014/pdf/D066.pdf |
