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Universal scan based JTAG compatible VLSI debug structure
Authors
	Ladnushkin M.S.
Date of publication
	2014
Abstract
	Design-for-test features and debug tools for modern VLSI designs were analyzed. The debug VLSI structure which allows serial access to all the states of the device triggers via the JTAG interface is presented. This debug structure is low-area (0,2%), all-around and reach high test coverage in scan mode.
Keywords
	VLSI debug, rejection, JTAG, scan, design-for-test, design-for-debug.
Library reference
	Ladnushkin M.S. Universal scan based JTAG compatible VLSI debug structure // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 2. P. 29-32.
URL of paper
	http://www.mes-conference.ru/data/year2014/pdf/D041.pdf