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| The two-phase 28-nm CMOS inverters in SET-tolerant logics |
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| Authors |
| | Katunin Yu.V. |
| | Stenin V.Ya. |
| Date of publication |
| | 2014 |
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| Abstract |
| | The single-event transients of the two-phase 28-nm CMOS inverters depends strongly on the capacitance between their differential inputs (outputs). When the capacitances of the differential coupling buses are below the threshold values, the critical charges of two-phase CMOS inverters are more than an order of magnitude larger than the critical charges of the traditional CMOS inverters. A layout technique that mitigates SETs in two-phase CMOS inverters has been proposed. |
| Keywords |
| | Two-phase logic, CMOS inverter, single nuclear particle, simulation, critical charge, layout technique |
| Library reference |
| | Katunin Yu.V., Stenin V.Ya. The two-phase 28-nm CMOS inverters in SET-tolerant logics // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 3. P. 141-144. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2014/pdf/D036.pdf |
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