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Automatic layout synthesis of standard cell layouts based on re-using existing transistor placement patterns and routing patterns
Authors
	Rozenfeld V.P.
	Smirnov Yu.G.
	Mazias R.L.
	Zhuravlev A.V.
Date of publication
	2012
Abstract
	In this paper we propose a method of automatic layout synthesis of CMOS standard cell layouts based on full or partial re-use of layout parts of existing cells that implement same or similar logic functions. The proposed approach allows to significantly reduce amount of used topological patterns and shortens time needed for standard cell layout synthesis.
Keywords
	CMOS standard cell, layout, synthesis, re-use, layout pattern, consistent placement, consistent routing
Library reference
	Rozenfeld V.P., Smirnov Yu.G., Mazias R.L., Zhuravlev A.V. Automatic layout synthesis of standard cell layouts based on re-using existing transistor placement patterns and routing patterns // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2012. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2012. P. 243-246.
URL of paper
	http://www.mes-conference.ru/data/year2012/pdf/D153.pdf