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Models and methods for SoC verification
Authors
	Hahanov V.I.
	Litvinova E.I.
	Guz O.A.
	Chumachenko S.V.
Date of publication
	2012
Abstract
	An infrastructure IP for verification of digital system-on-chip based on parallel analysis of tabular or matrix data structures in a vector logic space by using multiprocessor architectures is proposed. The models and methods for verification, embedded diagnosis and repairing components of digital systems, where the solution quality is evaluated by nonarithmetic metric of Boolean vectors interaction, are described.
Keywords
	Multiprocessor, vector logic analysis, quality criterion, verification, diagnosis of digital components, process model for detecting faults
Library reference
	Hahanov V.I., Litvinova E.I., Guz O.A., Chumachenko S.V. Models and methods for SoC verification // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2012. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2012. P. 22-29.
URL of paper
	http://www.mes-conference.ru/data/year2012/pdf/D134.pdf