| Instruction scheduling for vector processors with variable vector length |
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| Authors |
| | Panteleev A.Yu. |
| Date of publication |
| | 2012 |
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| Abstract |
| | The report describes the instruction scheduling unit for a vector processor with variable vector length. Any instruction can be launched before full completion of the previous instruction. Analytic expressions are presented which compute the execution time of test programs based on pipeline depth and scheduler parameters. These expressions accurately match the experimental results obtained from the simulation of the RTL model of a vector processor with such scheduler. Early instruction launch can improve performance by 1.1-1.9 times in some cases. |
| Keywords |
| | vector processor, variable vector length, instruction scheduler |
| Library reference |
| | Panteleev A.Yu. Instruction scheduling for vector processors with variable vector length // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2012. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2012. P. 395-398. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2012/pdf/D127.pdf |
