| Programmable High Frequency PLL Divider |
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| Authors |
| | Bystritsky S.A. |
| | Klyukin V.I. |
| | Bormontov E.N. |
| Date of publication |
| | 2012 |
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| Abstract |
| | This article presents high-speed divider demanded in high frequency integrated circuits. Divider's structure is oriented to use in programmable PLLs. Divider implemented in CMOS technology with dynamic D-flip-flops as a basic cell. Simulation shows input frequencies can exceed 1 GHz. |
| Keywords |
| | frequency divider, PLL, LFSR, dynamic logic |
| Library reference |
| | Bystritsky S.A., Klyukin V.I., Bormontov E.N. Programmable High Frequency PLL Divider // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2012. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2012. P. 324-327. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2012/pdf/D108.pdf |
