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Methodology for creating design-for-test for CMOS VLSI
Authors
	Ladnushkin M.S.
Date of publication
	2012
Abstract
	A complex methodology of developing design-for-test for CMOS VLSI which assumes creating hierarchical scan compression architecture using behavioral memory models for detecting shadow faults, utilization Pattern Mapping for apply tests to small memories in conjunction with MBIST for rest of memories was suggested. Implementing this methodology results in reducing by 20% time of developing design-for-test, increasing test coverage by 5%, lifting efficiency using Pattern Map technology and MBIST and redusing design area by 0,05%.
Keywords
	Rejection, test, chip, RAM, scan chain, Pattern Map.
Library reference
	Ladnushkin M.S. Methodology for creating design-for-test for CMOS VLSI // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2012. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2012. P. 485-488.
URL of paper
	http://www.mes-conference.ru/data/year2012/pdf/D96.pdf