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| Dual-Core Heterogeneous System-on-Chip “Elbrus-2S+” |
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| Authors |
| | Isaev M.V. |
| | Kozhin A.S. |
| | Kostenko V.O. |
| | Polyakov N.Y. |
| | Sakhin Yu.H. |
| Date of publication |
| | 2012 |
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| Abstract |
| | This paper describes architecture features and technical specification of new processor which consists of two cores, cache, system and peripheral controllers and DSP-cluster. The main problems and engineering solution leading to project performing are analyzed. |
| Keywords |
| | Elbrus, architecture, multi-core, dual-core, DSP, radiolocation, system-on-chip, SoC, core integration, memory management, memory subsystem, heterogeneous systems. |
| Library reference |
| | Isaev M.V., Kozhin A.S., Kostenko V.O., Polyakov N.Y., Sakhin Yu.H. Dual-Core Heterogeneous System-on-Chip “Elbrus-2S+” // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2012. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2012. P. 399-404. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2012/pdf/D93.pdf |
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