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| Analysis of efficiency of complex use low-power techniques for blocks of digital VLSI |
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| Authors |
| | Lobanova A.Y. |
| Date of publication |
| | 2012 |
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| Abstract |
| | In this work, low-power techniques (clock gating, gate level optimization, operand isolation) are considered. Optimal combinations of methods are detected for controller of microprocessor's external memory considering area and performance using 250nm, 130nm, 90nm technologies. |
| Keywords |
| | low-power techniques, clock gating, gate level optimization, operand isolation, microprocessor |
| Library reference |
| | Lobanova A.Y. Analysis of efficiency of complex use low-power techniques for blocks of digital VLSI // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2012. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2012. P. 507-510. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2012/pdf/D91.pdf |
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