| Arithmetical algorithms of the coding system of 1 from 4 with an active zero and estimation of the parameters of high-speed performance and occupied area of the unit of summation |
|
|
| Authors |
| | Losev V.V. |
| | Orlov D.V. |
| Date of publication |
| | 2012 |
|
| Abstract |
| | The given article is devoted to the implementation of arithmetical algorithms of the coding system of 1 from 4 with an active zero. Synthesis of the behavioral description of the unit of the adder was executed according to the offered algorithm. A test structure on language Verilog-HDL was implemented to check, debug and examine the obtained structure. Unit of summation was examined on high-speed performance and its occupied area. |
| Keywords |
| | synthesis, coding system of 1 from 4 with an active zero. |
| Library reference |
| | Losev V.V., Orlov D.V. Arithmetical algorithms of the coding system of 1 from 4 with an active zero and estimation of the parameters of high-speed performance and occupied area of the unit of summation // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2012. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2012. P. 525-528. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2012/pdf/D77.pdf |
