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An Efficient Router Bufferization for Network-on-Chip Design

Authors
 Medvedev I.A.
Date of publication
 2012

Abstract
 Evolution of microelectronic technology techniques together with requirements of electronic devices productivity growth lead to changing of interconnect development accents and priorities. Networks-on-Chip are becoming more popular. In this paper presented experience of development interconnect platform with parameterization on bufferization type and size of network. Bufferization with different location in the router and different depth of its FIFO queues has qualitative and quantative analysed for network interconnects with varied numbers of nodes.
Keywords
 multicore processors; scalability of interconnect; network-on-chip; virtual channels; channels bufferization
Library reference
 Medvedev I.A. An Efficient Router Bufferization for Network-on-Chip Design // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2012. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2012. P. 445-450.
URL of paper
 http://www.mes-conference.ru/data/year2012/pdf/D38.pdf

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