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Using convertible addressing modes to improve performance of DSP co-processors in a multicore SoC
Authors
	Panteleev A.Yu.
	Shagurin I.I.
Date of publication
	2012
Abstract
	In this report, a new way to address vector memory is proposed. This approach is designed to convert data addressing modes for improving the performance of digital signal processing (DSP) algorithms. The structure of a vector-pipeline co-processor (VPC) with addressing modes conversion is described. This co-processor performs the most common DSP routines with great efficiency: for example, during FFT-256 computation, the floating-point units are utilized at 89%. The features of this VPC architecture, its instruction set, and implementation of such algorithms as FFT, convolution and vector-matrix multiplication are described. The report presents the results of VPC synthesis for DSP-targeted systems on chip (SoC).
Keywords
	vector-pipeline co-processor, addressing modes conversion, digital signal processing, fast Fourier transform (FFT)
Library reference
	Panteleev A.Yu., Shagurin I.I. Using convertible addressing modes to improve performance of DSP co-processors in a multicore SoC // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2012. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2012. P. 389-394.
URL of paper
	http://www.mes-conference.ru/data/year2012/pdf/D36.pdf