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Low power FSM’s synthesis based on combined structural model
Authors
	Salauyou V.V.
Date of publication
	2012
Abstract
	A method of a low power FSM’s synthesis based on combined structural model ADE is considered. The method allows to use the flip-flops of the input and output buffers as FSM’s memory elements. The method is applicable at realization of FSMs on FPGA/CPLD and system on programmable chips. Results of experimental researches have shown that the offered approach, on the average, surpasses method NOVA in 2,41 times (on occasion – in 7,3 times), and method JEDI in 1,96 times (on occasion – in 5,43 times). In the conclusion it is underlined features of practical use of the considered method, and also on perspective directions of the further researches in this field.
Keywords
	low power; power consumption; finite state machines; FSM; logic synthesis; programmed logic devices; FPGA; CPLD; system programmable chip; state assign; structural models.
Library reference
	Salauyou V.V. Low power FSM’s synthesis based on combined structural model // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2012. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2012. P. 79-82.
URL of paper
	http://www.mes-conference.ru/data/year2012/pdf/D31.pdf