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Modeling and Verification of Communication Fabrics in System on Chip Design
Authors
	Gotmanov A.N.
	Kishinevsky M.A.
	S. Chatterjee
Date of publication
	2012
Abstract
	One of the ways to ensure system correctness early in the design cycle is to build an abstract model and establish its properties in a formal proof. In this paper we consider verification of microarchitectural models of communication fabrics constructed from a limited set of basic blocks with simple semantics. We show that analysis of model structure simplifies proofs of its properties including deadlock-freedom. Proposed methods were successfully applied to verify microarchitectures of industrials systems on chip, when alternative approaches failed to provide results.
Keywords
	modeling, formal verification, xMAS, deadlocks, communication fabrics, microarchitecture, systems on chip.
Library reference
	Gotmanov A.N., Kishinevsky M.A., S. Chatterjee Modeling and Verification of Communication Fabrics in System on Chip Design // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2012. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2012. P. 61-66.
URL of paper
	http://www.mes-conference.ru/data/year2012/pdf/D28.pdf